The present invention relates to a device for detecting output data of a counter and more particularly to the one in which data to be detected previously stored in a separate memory and the data stored therein is compared with output data of the counter for the detection of the counter output.
One of the prior art counter output detectors is shown in FIG. 1. A first counter of which the output data are detected and the reference numeral attached thereto is 1, counts input pulses CP.sub.1 applied thereto. The counter 1 includes first binary memory units 1a to 1d outputting binary output signals Q.sub.11 to Q.sub.14 ("1" or "0"). A second counter designated by reference numeral 2 in which reference data are stored includes second binary memory units 2a to 2d outputting binary output signals Q.sub.21 to Q.sub.24. The second counter 2 stores a given reference data when the input pulses CP.sub.2 are counted by a predetermined number. Each exclusive OR circuit (EXOR) 3, 4, 5 and 6 receives a pair of signals (Q.sub.11, Q.sub.21), (Q.sub.12, Q.sub.22), (Q.sub.13, Q.sub.23), and (Q.sub.14, Q.sub.24), respectively, and the outputs of these EXOR circuits are applied to an OR circuit 7. When data stored in the first and second counters are coincident to each other, the OR circuit 7 outputs a coincident signal Exo. In such a circuit arrangement including EXOR circuits 3 to 6 and OR circuit 7, a number of gate elements are necessarily used so that a signal delay is great, and therefore such the circuit arrangement becomes impracticable as the frequency of the CP.sub.1 becomes large. Particularly, this disadvantage becomes distinctive when the number of the first and second binary memory units increases.
Accordingly, an object of the present invention is to provide a device for detecting the output data of a counter with the minimum number of gate elements constituting the data detector and with the minimum signal delay.